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R8C/13 Datasheet(PDF) 137 Page - Renesas Technology Corp |
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R8C/13 Datasheet(HTML) 137 Page - Renesas Technology Corp |
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137 / 224 page ![]() Rev.1.20 Jan 27, 2006 page 126 of 205 REJ09B0111-0120 R8C/13 Group AD control register 0 SymbolAddressAfter reset ADCON000D616 00000XXX2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit See Note 4. CH0 Bit symbol Bit name Function CH1 CH2 AD operation mode select bit(2) 0 : One-shot mode 1 : Repeat mode MD ADST A/D conversion start flag 0 : A/D conversion disabled 1 : A/D conversion started Frequency select bit 0(3) 0 : fAD/4 is selected 1 : fAD/2 is selected CKS0 RW NOTES: 1. If the ADCON register is rewritten during A/D conversion, the conversion result is indeterminate. 2. When changing A/D operation mode, set analog input pin again. 3. This bit is valid when the CKS1 bit in the ADCON1 register is set to “0”. 4. The analog input pin can be selected by a combination of the CH2 to CH0 bits and ADGSEL0 bit as follows: 0 0: Port P0 group selected (AN0 to AN7) 1: Port P1 group selected (AN8 to AN11) AD input group select bit(4) RW RW RW RW RW RW RW RW ADGSEL0 Set to “0” Reserved bit (b5) AD control register 1 Symbol AddressAfter reset ADCON100D716 0016 Bit nameFunction Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result is indeterminate. 2. In repeat mode, the BITS bit must be set to “0” (8-bit mode). 3. The φAD frequency must be 10 MHz or less. 4. If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting A/D conversion. BITS 8/10-bit mode select bit(2) 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit(4) 0 : Vref not connected 1 : Vref connected Frequency select bit 1(3) CKS1 0 0 0 0 0 Set to “0” Reserved bit (b2-b0) RW RW RW RW RW RW Set to “0” Reserved bit (b6-b7) 0 : CKS0 bit in ADCON0 register is valid 1 : fAD is selected CH2 to CH0ADGSEL0=0ADGSEL0=1 0002 0012 0102 0112 1002 1012 1102 1112 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Avoid these settings (1) (1) Figure 14.2 ADCON0 Register and ADCON1 Register 14. A/D Converter |
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