R8CSLASH13 datasheet(134/224 Pages) RENESAS

134 / 224 page

Rev.1.20

Jan 27, 2006

page 123 of 205

REJ09B0111-0120

R8C/13 Group

13.2 Clock Asynchronous Serial I/O (UART) Mode

13.2.3 Bit Rate

Divided-by-16 of frequency by the UiBRG (i=0 to 1) register in UART mode is a bit rate.

• When selecting internal clock

Setting value to the UiBRG register =

–1

fj : Count source frequency of the UiBRG register (f1SIO, f8SIO and f32SIO)

• When selecting external clock

Setting value to the UiBRG register =

–1

fEXT : Count source frequency of the UiBRG register (external clock)

Bit Rate ✕ 16

fEXT

Bit Rate ✕ 16

Figure 13.11 Calculation Formula of UiBRG (i=0 to 1) Register Setting Value

Table 13.7 Bit Rate Setting Example in UART Mode

Bit Rate

BRG

System Clock = 20MHz

System Clock = 8MHz

(bps)

Count Source

BRG Setting Value Actual Time(bps)

Error(%)

BRG Setting Value Actual Time(bps)

Error(%)

1200

129 (8116)

1201.92

0.16

51 (3316)

1201.92

0.16

2400

64 (4016)

2403.85

0.16

25 (1916)

2403.85

0.16

4800

32 (2016)

4734.85

–1.36

12 (0C16)

4807.69

0.16

9600

129 (8116)

9615.38

0.16

51 (3316)

9615.38

0.16

14400

86 (5616)

14367.82

–0.22

34 (2216)

14285.71

–0.79

19200

64 (4016)

19230.77

0.16

25 (1916)

19230.77

0.16

28800

42 (2A16)

29069.77

0.94

16 (1016)

29411.76

2.12

31250

39 (2716)

31250.00

0.00

15 (0F16)

31250.00

0.00

38400

32 (2016)

37878.79

–1.36

12 (0C16)

38461.54

0.16

51200

23 (1716)

52083.33

1.73

9 (0916)

50000.00

–2.34

R8C/13 Datasheet(PDF) 134 Page - Renesas Technology Corp

R8C/13 Datasheet(HTML) 134 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL