R8CSLASH13 datasheet(135/224 Pages) RENESAS

135 / 224 page

Rev.1.20

Jan 27, 2006

page 124 of 205

REJ09B0111-0120

R8C/13 Group

14. A/D Converter

The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive

coupling amplifier. The analog inputs share the pins with P00 to P07 and P10 to P13. Therefore, when

using these pins, make sure the corresponding port direction bits are set to “0” (input mode).

When not using the A/D converter, set the VCUT bit to “0” (Vref unconnected), so that no current will flow

from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.

The result of A/D conversion is stored in the AD register.

Table 14.1 shows the performance of the A/D converter. Figure 14.1 shows a block diagram of the A/D

converter, and Figures 14.2 and 14.3 show the A/D converter-related registers.

Table 14.1 Performance of A/D converter

Item

Performance

Method of A/D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage(1)

0V to Vref

Operating clock

φAD(2)

AVCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD

AVCC = 3V divide-by-2 of fAD, divide-by-4 of fAD

Resolution

8-bit or 10-bit (selectable)

Integral nonlinearity error

AVcc = Vref = 5V

• 8-bit resolution ±2 LSB

• 10-bit resolution ±3 LSB

AVcc = Vref = 3.3 V

• 8-bit resolution ±2 LSB

• 10-bit resolution ±5 LSB

Operating modes

One-shot mode and repeat mode(3)

Analog input pins

12 pins (AN0 to AN11)

A/D conversion start condition ADST bit in ADCON0 register is set to “1” (A/D conversion starts)

Conversion speed per pin • Without sample and hold function

8-bit resolution: 49

φAD cycles, 10-bit resolution: 59 φAD cycles

• With sample and hold function

8-bit resolution: 28

φAD cycles, 10-bit resolution: 33 φAD cycles

NOTES:

1. Does not depend on use of sample and hold function.

2. The frequency of

φAD must be 10 MHz or less.

When AVcc is less than 4.2V,

φAD must be fAD/2 or less by dividing fAD.

Without sample and hold function, the

φAD frequency should be 250 kHz or more.

With the sample and hold function, the

φAD frequency should be 1 MHz or more.

3. In repeat mode, only 8-bit mode can be used.

14. A/D Converter

R8C/13 Datasheet(PDF) 135 Page - Renesas Technology Corp

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