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R8C/13 Datasheet(PDF) 132 Page - Renesas Technology Corp |
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R8C/13 Datasheet(HTML) 132 Page - Renesas Technology Corp |
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132 / 224 page  Rev.1.20 Jan 27, 2006 page 121 of 205 REJ09B0111-0120 R8C/13 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode TxDi Transfer clock UiC1 register TE bit UiC1 register TI bit UiC0 register TXEPT bit SiTIC register IR bit Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO) fEXT: frequency of UiBRG count source (external clock) n: value set to UiBRG i: 0, 1 “1” “0” “1” “0” “1” “0” “1” “0” The above timing diagram applies to the case where the register bits are set as follows: • UiMR register PRYE bit = 1 (parity enabled) • UiMR register STPS bit = 0 (1 stop bit) • UiIRS bit = 1 (an interrupt request occurs when transmit completed): Set to “0” when interrupt request is accepted, or set by a program D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST PSP D0 D1 ST Tc SP Start bit Parity bit Stop bit Stopped pulsing because the TE bit = “0” Write data to UiTB register Transferred from UiTB register to UARTi transmit register • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 13.9 Transmit Operation TxDi Transfer clock UiC1 register TE bit UiC1 register TI bit UiC0 register TXEPT bit SiRIC register IR bit “0” “1” “0” “1” “0” “1” “0” “1” The above timing diagram applies to the case where the register bits are set as follows: • UiMR register PRYE bit = 0 (parity disabled) • UiMR register STPS bit = 1 (2 stop bits) • UiIRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty) Tc D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 D2 D3 D4 D5 D6 D7 ST D8 D0 D1 ST SPSP SP SP Write data to UiTB register Transferred from UiTB register to UARTi transmit register Set to “0” when interrupt request is accepted, or set by a program Stop bit Stop bit Start bit Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO) fEXT: frequency of UiBRG count source (external clock) n: value set to UiBRG i: 0, 1 |
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