R8CSLASH20 datasheet(325/501 Pages) RENESAS

325 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 309 of 458

REJ09B0250-0200

Figure 16.20

Example of Clock Synchronous Serial I/O with Chip Select Operation during Data

Reception (4-Wire Bus Communication Mode)

SSCK

SSI

• When CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)

SCS

(Output)

SSCK

• When CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)

CPHS and CPOS: Bit in SSMR register

1 frame

RDRF bit in

SSSR register

RSSTP bit in

SSCRH register

Dummy read in

SSRDR register

Process by

program

1 frame

High-impedance

SCS

(Output)

Data read in SSRDR

RXI interrupt request

is generated

RXI interrupt request

is generated

Data read in SSRDR

RXI interrupt request

is generated

SSI

1 frame

RDRF bit in

SSSR register

RSSTP bit in

SSCRH register

Dummy read in

SSRDR register

Process by

program

1 frame

Data read in SSRDR

RXI interrupt request

is generated

RXI interrupt request

is generated

RXI interrupt request

is generated

Set RSSTP

bit to 1

Data read in SSRDR

Set RSSTP

bit to 1

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