R8CSLASH20 datasheet(323/501 Pages) RENESAS

323 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 307 of 458

REJ09B0250-0200

Figure 16.19

Example of Clock Synchronous Serial I/O with Chip Select Operation during Data

Transmission (4-Wire Bus Communication Mode)

TDRE bit in

SSSR register

TEND bit in

SSSR register

Data write to SSTDR register

Process by

program

SSCK

SSO

• When CPHS bit = 0 (data change at even edges), CPOS bit = 0 (“H” when clock stops)

SCS

(Output)

SSCK

• When CPHS bit = 1 (data change at even edges), CPOS bit = 0 (“H” when clock stops)

CPHS, CPOS: Bits in SSMR register

1 frame

TDRE bit in

SSSR register

TEND bit in

SSSR register

Data write to SSTDR register

Process by

program

1 frame

High-impedance

SCS

(output)

TXI interrupt request is

generated

SSO

1 frame

TXI interrupt request is

generated

TEI interrupt request is

generated

TEI interrupt request is

generated

TXI interrupt request is

generated

TXI interrupt request is

generated

R8C/20 Datasheet(PDF) 323 Page - Renesas Technology Corp

R8C/20 Datasheet(HTML) 323 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL