R8CSLASH20 datasheet(320/501 Pages) RENESAS

320 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 304 of 458

REJ09B0250-0200

16.2.6

Operation in 4-Wire Bus Communication Mode

4-wire bus communication mode is a mode which communicates with the 4-wire bus; a clock line, data input

line, data output line and chip select line. This mode includes bidirectional mode in which the data input line

and data output line function as a single pin.

The data input line and output line are changed according to the setting of the MSS bit in the SSCRH register

and the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and

SS Shift Register. In this mode, association between the clock polarity, phase and data can be set by the CPOS

and CPHS bits in the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock

Polarity, Phase, and Data.

When the clock synchronous serial I/O with chip select is set as a master device, the chip select line controls

output. When the clock synchronous serial I/O with chip select is set as a slave device, the chip select line

controls input. When the clock synchronous serial I/O with chip select is set as master device, the chip select

line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in the SSMR2

the SCS pin as an input pin by setting the CSS1 and CSS0 bits in the SSMR2 register to 01b.

In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is

performed using the MSB-first.

16.2.6.1

Initialization in 4-Wire Bus Communication Mode

Figure 16.18 shows an Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive, set

the TE bit in the SSER register to 0 (disables transmit) and the RE bit in the SSER register to 0 (disables

receive) and initialize the clock synchronous serial I/O with chip select.

When communication mode and format are changed, set the TE bit to 0 and the RE bit to 0 before changing.

Setting the RE bit to 0 does not change the contents of the RDRF and ORER flags, and the contents of the

SSRDR register.

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