R8CSLASH20 datasheet(292/501 Pages) RENESAS

292 / 501 page

R8C/20 Group, R8C/21 Group

15. Serial Interface

Rev.2.00 Aug 27, 2008

Page 276 of 458

REJ09B0250-0200

15.2

Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmit and receive data after setting the desired bit rate and transfer data format.

Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode.

i = 0 or 1

NOTE:

1. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR

bit in the S0RIC register remains unchanged.

Table 15.4

UART Mode Specifications

Item

Specification

Transfer Data Formats

• Character bit (transfer data): selectable from 7, 8 or 9 bits

• Start bit: 1 bit

• Parity bit: selectable from odd, even, or none

• Stop bit: selectable from 1 or 2 bits

Transfer Clocks

• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n + 1))

fj = f1, f8, f32 n = setting value in U0BRG register: 00h to FFh

• CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))

fEXT: Input from CLK0 pin n = setting value in UiBRG register: 00h to FFh

Transmit Start Conditions

• Before transmit starts, the following are required

- TE bit in UiC1 register is set to 1 (transmit enabled)

- TI bit in UiC1 register is set to 0 (data in UiTB register)

Receive Start Conditions

• Before receive starts, the following are required

- RE bit in UiC1 register is set to 1 (receive enabled)

- Detects start bit

Interrupt Request

Generation Timing

• When transmitting, one of the following conditions can be selected

- UiIRS bit is set to 0 (transmit buffer empty):

when transferring data from the UiTB register to UARTi transmit register

(when transmit starts)

- UiIRS bit is set to 1 (transfer ends):

when serial interface completes transmitting data from the UARTi

transmit register

• When receiving

When transferring data from the UARTi receive register to UiRB register

(when receive ends)

Error Detection

•Overrun error(1)

This error occurs if serial interface starts receiving the following data

before reading the UiRB register and receiving the bit one before the last

stop bit of the following data

• Framing error

This error occurs when the number of stop bits set are not detected

• Parity error

This error occurs when parity is enabled, the number of 1’s in parity and

character bits do not match the number of 1’s set

• Error sum flag

This flag is set is set to 1 when any of the overrun, framing, and parity

errors is generated

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