R8CSLASH20 datasheet(289/501 Pages) RENESAS

289 / 501 page

R8C/20 Group, R8C/21 Group

15. Serial Interface

Rev.2.00 Aug 27, 2008

Page 273 of 458

REJ09B0250-0200

Figure 15.7

Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode

Transfer clock

TE bit in U0C1

TXD0

• Example of transmit timing (when internal clock is selected)

Set data in U0TB register

Transfer from U0TB register to UART0 transmit register

CLK0

TCLK

Stop pulsing because the TE bit is set to 0

TC = TCLK = 2(n+1)/fi

fi: Frequency of UiBRG count source (f1, f8, f32)

n: Setting value to UiBRG register

The above applies under the following settings:

• CKDIR bit in U0MR register = 0 (internal clock)

• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)

• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty)

Set to 0 when interrupt request is acknowledged, or set by a program

Write dummy data to U0TB register

Transfer from U0TB register to UART0 transmit register

1/fEXT

Receive data is taken in

Read out from U0RB register

Transfer from UART0 receive register to

U0RB register

TI bit in U0C1

TXEPT bit in

U0C0 register

IR bit in S0TIC

Set to 0 when interrupt request is acknowledged, or set by a program

• Example of receive timing (when external clock is selected)

RE bit in U0C1

TE bit in U0C1

TI bit in U0C1

RI bit in U0C1

IR bit in S0RIC

CLK0

RXD0

The above applies under the following settings:

• CKDIR bit in U0MR register = 1 (external clock)

• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)

The following conditions are met when “H” is applied to the CLK0 pin before receiving data:

• TE bit in U0C1 register = 1 (enables transmit)

• RE bit in U0C1 register = 1 (enables receive)

• Write dummy data to the U0TB register

fEXT: Frequency of external clock

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