IS25LP256D-RLLA3 datasheet(155/174 Pages) ISSI

155 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

155

Rev A6

04/15/2019

8.62 PROGRAM PASSWORD OPERATION (PGPWD, E8h)

Before the Program Password (PGPWD) command can be accepted by the device, a Write Enable (WREN)

command must be issued and decoded by the device which sets the Write Enable Latch (WEL) to enable the

PGPWD operation. The password can only be programmed before the Password Mode is selected by programming

the Password Protection Mode bit to “0” in the ASP Register (ASP[2]). After the Password Protection Mode is

selected the PGPWD command is ignored.

The PGPWD command is entered by driving CE# low, followed by the instruction code and the password data

bytes, least significant byte first, most significant bit of each byte first. The password is 64bits in length.

CE# must be driven high after the 64th bit of data has been latched. If not, the PGPWD command is not executed.

As soon as CE# is driven high, the PGPWD operation is initiated. While the PGPWD operation is in progress, the

Status Register or Extended Read Register may be read to check the value of the Write In Progress (WIP) bit. The

WIP bit is “1” during the PGPWD operation, and is “0” when it is completed. When the PGPWD operation is

completed, the Write Enable Latch (WEL) is set to “0”. The maximum clock frequency for the PGPWD command

is the same with Fast Read Operation.

Figure 8.144 Program Password Sequence In SPI Mode

Instruction = E8h

CE #

SCK

...

Mode 3

Mode 0

...

st byte Data In

nd byte Data In

...

th byte Data In

High Impedence

Figure 8.145 Program Password Sequence In QPI Mode

E8h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

st byte

Data In

nd byte

Data In

...

th byte

Data In

...

IS25LP256D-RLLA3 Datasheet(PDF) 155 Page - Integrated Silicon Solution, Inc

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