IS25LP256D-RLLA3 datasheet(152/174 Pages) ISSI

152 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

152

Rev A6

04/15/2019

8.59 WRITE PPB LOCK BIT OPERATION (WRPLB, A6h)

The Write PPB Lock Bit (WRPLB) command clears the PPB Lock (PPBLK) bit to zero. Before the WRPLB command

can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,

which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The WRPLB command is entered by driving CE# low, followed by the instruction code. CE# must be driven high

after the eighth bit of instruction has been latched in. If not, the WRPLB command is not executed. As soon as CE#

is driven high, the WRPLB operation is initiated. While the WRPLB operation is in progress, the Status Register or

Extended Read Register may still be read to check the value of the Write In

Progress (WIP) bit. The WIP bit is “1”

during the WRPLB operation, and is “0” when it is completed. When the WRPLB operation is completed, the WEL

is set to “0”. The maximum clock frequency for the WRPLB command is the same with Fast Read Operation.

Figure 8.138 Write PPB Lock Bit Sequence In SPI Mode

Instruction = A6h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.139 Write PPB Lock Bit Sequence In QPI Mode

A6h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

IS25LP256D-RLLA3 Datasheet(PDF) 152 Page - Integrated Silicon Solution, Inc