IS25LP256D-RLLA3 datasheet(24/174 Pages) ISSI

24 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

WIP bit: The definition of the WIP bit is exactly same as the one of Status Register.

PROT_E bit: The Protection Error bit indicates whether an Erase or Program operation has attempted to modify a

protected array sector or block, or to access a locked Information Row region. When the bit is s

et to “1” it indicates

that there was an error or errors in previous Erase or Program operations. See Table 6.15 for details.

P_ERR bit: The Program Error bit indicates whether a Program operation has succeeded or failed, or whether a

Program operation has attempted to program a protected array sector/block or a locked Information Row region.

When the bit is set to

“1” it indicates that there was an error or errors in previous Program or Write/Set Non-Volatile

Table 6.15 Instructions to set PROT_E bit and P_ERR bit

Instructions

Description

PP/4PP/PPQ/4PPQ/PGPPB/

4PGPPB/PGPWD

The commands will set the P_ERR if there is a failure in the operation. Attempting to program

within the protected array sector/block or within an erase suspended sector/block will result in

a programming error with P_ERR and PROT_E

set to “1”.

IRP

The command will set the P_ERR if there is a failure in the operation. In attempting to program

within a locked Information Row region, the operation will fail with P_ERR and PROT_E set to

PGASP

The command will set the P_ERR if there is a failure in the operation. Attempting to program

ASPR[2:1] after the Protection Mode is selected or attempting to program ASPR[2:1] = 00b

will result in a programming error with P_ERR and PROT_E

set to “1”.

UNPWD

If the UNPWD command supplied password does not match the hidden internal password, the

UNPWD operation fails in the same manner as a programming operation on a protected

sector/block and sets the P_ERR and PROT_E

to “1”.

WRSR/WRABR/SRPNV/

SERPNV/WRBRNV

The update process for the non-volatile register bits involves an erase and a program operation

on the non-volatile register bits. If either the erase or program portion of the update fails, the

related error bit (P_ERR)

will be set to “1”.

Only for WRSR command, when Status Register is write-protected by SRWD bit and WP# pin,

attempting to write the register will set PROT_E to “1”.

WRFR

The commands will set the P_ERR if there is a failure in the operation.

SER/4SER/BER32K/

4BER32K/BER64K/

4BER64K/CER/IRER/ERPPB

PROT_E will be set to “1” when the user attempts to erase a protected main memory

sector/block or a locked Information Row region. Chip Erase (CER) command will set PROT_E

if any blocks are protected by Block Protection bits (BP3~BP0). But Chip Erase (CER)

command will not set PROT_E if sectors/blocks are protected by ASP (DYB bits or PPB bits)

only.

Notes:

OTP bits in the Function Register and TBPARM (OTP bit) in the ASP Register may only be programmed to “1”.

Writing of the bits back to “0” is ignored and no error is set.

2. Read only bits and partially protected bits by FREEZE bit in registers are never modified by a command so that the

corresponding bits in the Write/Set Register command data byte are ignored without setting any error indication.

3. Once the PROT_E and P_ERR error

bits are set to “1”, they remains set to “1” until they are cleared to “0” with a

Clear Extended Read Register (CLERP) command. This means that those error bits must be cleared through the

CLERP command. Alternatively, Hardware Reset, or Software Reset may be used to clear the bits.

Any further command will be executed even though the error bits are set to “1”.

IS25LP256D-RLLA3 Datasheet(PDF) 24 Page - Integrated Silicon Solution, Inc

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