IS25LP256D-RLLA3 datasheet(96/174 Pages) ISSI

96 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

Rev A6

04/15/2019

8.26 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h)

Set Read Parameter Bits

This device supports configurable burst length and dummy cycles in both SPI and QPI mode by setting three bits

(P2, P1, P0) and four bits (P6, P5, P4, P3) within the Read Register, respectively. To set those bits the SRPNV

and SRPV operation instruction are used. Details regarding burst length and dummy cycles can be found in Table

6.9, Table 6.10, and Table 6.11. HOLD#/RESET# function selection (P7) bit in the Read Register can be set with

the SRPNV and SRPV operation as well, in order to select HOLD#/RESET# pin as RESET# or HOLD#.

For the device with dedicated RESET# pin (or ball), RESET# pin (or ball) will be a separate pin (or ball) and it is

independent of the P7 bit setting in Read Register.

SRPNV is used to set the non-volatile Read Register, while SRPV is used to set the volatile Read Register.

Note: When SRPNV is executed, the volatile Read Register is set as well as the non-volatile Read Register.

Figure 8.59 Set Read Parameters Sequence In SPI Mode

Instruction = 65h or C0h/63h

CE #

SCK

Data In

Mode 3

Mode 0

High Impedence

Figure 8.60 Set Read Parameters Sequence In QPI Mode

65h or

C0h/63h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In

IS25LP256D-RLLA3 Datasheet(PDF) 96 Page - Integrated Silicon Solution, Inc