IS25LP256D-RLLA3 datasheet(150/174 Pages) ISSI

150 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

150

Rev A6

04/15/2019

8.57 PROGRAM ASP OPERATION (PGASP, 2Fh)

Before the Program ASP (PGASP) command can be accepted by the device, a Write Enable (WREN) command

must be issued. After the WREN command has been decoded, the device will set the Write Enable Latch (WEL) in

the Status Register to enable any write operations.

The PGASP command is entered by driving CE# low, followed by the instruction code and two data bytes, least

significant byte first, most significant bit of each byte first. The ASP Register is two data bytes in length. The PGASP

command affects the Write In Progress (WIP) bit in the same manner as any other programming operation.

CE# input must be driven high after the sixteenth bit of data has been latched in. If not, the PGASP command is

not executed. As soon as CE# is driven high, the PGASP operation is initiated. While the PGASP operation is in

progress, the Status Register or the Extended Read Register may be read to check the value of WIP bit. The WIP

bit is “1” during the PGASP operation, and is “0” when it is completed. When the PGASP operation is completed,

the WEL is set to “0”.

Figure 8.134 Program ASP Sequence In SPI Mode

Instruction = 2Fh

CE #

SCK

...

Mode 3

Mode 0

st byte Data In

High Impedence

...

nd byte Data In

Figure 8.135 Program ASP Sequence In QPI Mode

2Fh

SCK

IO[3:0]

Mode 3

Mode 0

st byte

Data In

nd byte

Data In

CE#

IS25LP256D-RLLA3 Datasheet(PDF) 150 Page - Integrated Silicon Solution, Inc