IS25LP256D-RLLA3 datasheet(146/174 Pages) ISSI

146 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

146

Rev A6

04/15/2019

8.54 PROGRAM PPB OPERATION (PGPPB, FDh or 4PGPPB, E3h)

Before the Program PPB (PGPPB/4PGPPB) command is sent, a Write Enable (WREN) command must be issued.

After the WREN command has been decoded, the device will set the Write Enable Latch (WEL) in the Status

FDh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

FDh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

E3h is followed by a 4-byte address (A31-A0)

The PGPPB/4PGPPB command is entered by driving CE# low, followed by the instruction code, followed by the

24-bit or 32-bit address selecting location zero within the desired sector/block as above.

The PGPPB/4PGPPB command affects the WIP bit in the same manner as any other programming operation. CE#

must be driven high after the last bit of address has been latched in. As soon as CE# is driven high, the

PGPPB/4PGPPB operation is initiated. While the PGPPB/4PGPPB operation is in progress, the Status Register or

Extended Read Register may be read to check the value of the Write In

Progress (WIP) bit. The WIP bit is “1”

during the PGPPB/4PGPPB

operation, and is “0” when it is completed. When the PGPPB/4PGPPB operation is

completed, the WEL is set to “0”.

Note: The high order address bits not used by 256M/128M must be zero. Data must be either 00h (protected) or FFh

(unprotected).

Figure 8.126 Program PPB Sequence In SPI Mode (FDh [EXTADD=0], 3-byte address)

Instruction = FDh

CE #

SCK

...

Mode 3

Mode 0

3-byte Address

High Impedence

Figure 8.127 Program PPB Sequence In SPI Mode (FDh [EXTADD=1] or E3h, 4-byte address)

Instruction = FDh/E3h

CE #

SCK

...

Mode 3

Mode 0

4-byte Address

High Impedence

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