IS25LP256D-RLLA3 datasheet(145/174 Pages) ISSI

145 / 174 page

IS25LP256D

IS25WP256D

Integrated Silicon Solution, Inc.- www.issi.com

145

Rev A6

04/15/2019

8.53 READ PPB OPERATION (RDPPB, FCh or 4RDPPB, E2h)

FCh (EXTADD=0) is followed by a 3-byte address (A23-A0) or

FCh (EXTADD=1) is followed by a 4-byte address (A31-A0) or

E2h is followed by a 4-byte address (A31-A0)

The instruction code is shifted into SI by the rising edges of the SCK signal, followed by the 24-bit or 32-bit address

selecting location zero within the desired sector/block as above. Then the 8-bit PPB Access Register contents are

shifted out on SO. The RDPPB/4RDPPB is supporting only SPI, not supporting QPI.

It is possible to read the same PPB Access Register continuously by providing multiples of eight bits. The address

of the PPB Access Register does not increment so this is not a means to read the entire PPB array. Each location

must be read with a separate Read PPB command. The maximum operating clock frequency for the Read PPB

command is the same with Fast Read Operation.

Note: The high order address bits not used by 256M/128M must be zero. Data must be either 00h (protected) or FFh

(unprotected).

Figure 8.124 Read PPB Sequence (FCh [EXTADD=0], 3-byte address)

Instruction = FCh

CE #

SCK

...

Mode 3

Mode 0

3-byte Address

Figure 8.125 Read PPB Sequence (FCh [EXTADD=1] or E2h, 4-byte address)

Instruction = FCh/E2h

CE #

SCK

...

Mode 3

Mode 0

4-byte Address

IS25LP256D-RLLA3 Datasheet(PDF) 145 Page - Integrated Silicon Solution, Inc