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LAN9500AI Datasheet(PDF) 20 Page - Microchip Technology |
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LAN9500AI Datasheet(HTML) 20 Page - Microchip Technology |
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20 / 213 page  LAN950x DS00001875A-page 20 2010 - 2015 Microchip Technology Inc. TABLE 3-5: USB PINS Num Pins Name Symbol Buffer Type Description 1 USB DMINUS USBDM AIO Note: The functionality of this pin may be swapped to USB DPLUS via the PORT_SWAP configuration strap. 1 USB DPLUS USBDP AIO Note: The functionality of this pin may be swapped to USB DMINUS via the PORT_SWAP configuration strap. 1 External USB Bias Resistor. USBRBIAS AI Used for setting HS transmit current level and on- chip termination impedance. Connect to an external 12K 1.0% resistor to ground. 1 USB PLL Supply VDDUSBPLL P This pin must be connected to VDDCORE for proper operation. Refer to Section 4.0, "Power Connections," on page 24 and the device reference schematics for additional connection information. 1 Crystal Input XI ICLK External 25 MHz crystal input. Note: This pin can also be driven by a single- ended clock oscillator. When this method is used, XO should be left unconnected 1 Crystal Output XO OCLK External 25 MHz crystal output. TABLE 3-6: ETHERNET PHY PINS Num Pins Name Symbol Buffer Type Description 1 Ethernet TX Data Out Negative TXN AIO The transmit data outputs may be swapped internally with receive data inputs when Auto-MDIX is enabled. 1 Ethernet TX Data Out Positive TXP AIO The transmit data outputs may be swapped internally with receive data inputs when Auto-MDIX is enabled. 1 Ethernet RX Data In Negative RXN AIO The receive data inputs may be swapped internally with transmit data outputs when Auto-MDIX is enabled. 1 Ethernet RX Data In Positive RXP AIO The receive data inputs may be swapped internally with transmit data outputs when Auto-MDIX is enabled. 1 PHY Interrupt (Internal PHY Mode) nPHY_INT O8 In internal PHY mode, this pin can be configured to output the internal PHY interrupt signal. Note: The internal PHY interrupt signal is active-high. PHY Interrupt (External PHY Mode) nPHY_INT IS (PU) In external PHY mode, the active-low signal on this pin is input from the external PHY and indicates a PHY interrupt has occurred. |
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