LAN9500AI datasheet(18/213 Pages) MICROCHIP

18 / 213 page

LAN950x

DS00001875A-page 18

 2010 - 2015 Microchip Technology Inc.

TABLE 3-4:

MISCELLANEOUS PINS

Num Pins

Name

Symbol

Buffer

Type

Description

PHY Select

PHY_SEL

(PD)

Selects whether to use the internal Ethernet PHY

or the external PHY connected to the MII port.

0 = Internal PHY is used.

1 = External PHY is used.

Note:

When in external PHY mode, the internal

PHY is placed into general power down

after a POR. Please Refer to Section 5.6,

"10/100 Internal Ethernet PHY," on

page 69 for details.

System Reset

nRESET

(PU)

This active-low pin allows external hardware to

reset the device.

Note:

(LAN9500A/LAN9500Ai ONLY):

This pin may be used to signal

PME_CLEAR when PME mode of

operation is in effect. Refer to Section

6.0, "PME Operation," on page 112 for

additional information.

Ethernet

Full-Duplex

Indicator LED

nFDX_LED

OD12

(PU)

This pin is driven low (LED on) when the Ethernet

link is operating in full-duplex mode.

General

Purpose I/O 8

GPIO8

IS/O12/

OD12

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

Note 1: (LAN9500A/LAN9500Ai ONLY):

This pin may be used to signal PME

when External PHY and PME modes of

operation

are

effect.

Refer

Section 6.0 “PME Operation” for addi-

tional information.

2: By default this pin is configured as a

GPIO.

Ethernet Link

Activity

Indicator LED

nLNKA_LED

OD12

(PU)

This pin is driven low (LED on) when a valid link is

detected. This pin is pulsed high (LED off) for

80mS whenever transmit or receive activity is

detected. This pin is then driven low again for a

minimum of 80mS, after which time it will repeat

the process if TX or RX activity is detected.

Effectively, LED2 is activated solid for a link. When

transmit or receive activity is sensed, LED2 will

function as an activity indicator.

General

Purpose I/O 9

GPIO9

IS/O12/

OD12

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

Note 1: (LAN9500A/LAN9500Ai ONLY):

This pin may serve as the PME_-

MODE_SEL input when External PHY

and PME modes of operation are in

effect. Refer to Section 6.0 “PME

Operation” for additional information.

2: By default this pin is configured as a

GPIO.

LAN9500AI Datasheet(PDF) 18 Page - Microchip Technology

LAN9500AI Datasheet(HTML) 18 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL