LAN9500AI datasheet(8/213 Pages) MICROCHIP

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LAN950x

DS00001875A-page 8

 2010 - 2015 Microchip Technology Inc.

2.2.1

OVERVIEW

The LAN950x is a high performance solution for USB to 10/100 Ethernet port bridging. With applications ranging from

embedded systems, set-top boxes, and PVRs, to USB port replicators, USB to Ethernet dongles, and test instrumenta-

tion, the device is targeted as a high performance, low cost USB/Ethernet connectivity solution.

The LAN950x contains an integrated 10/100 Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device controller, 10/100

Ethernet MAC, TAP controller, EEPROM controller, and a FIFO controller with a total of 30 KB of internal packet buffer-

ing. Two KB of buffer memory are allocated to the Transaction Layer Interface (TLI), while 28 KB are allocated to the

FIFO Controller (FCT).

The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed standard. The device

implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.

The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is compliant with the

IEEE 802.3 and IEEE 802.3u standards. An external MII interface provides support for an external Fast Ethernet PHY,

HomePNA, and HomePlug functionality.

Multiple power management features are provided, including various low power modes and “Magic Packet”, “Wake On

LAN”, and “Link Status Change” wake events. These wake events can be programmed to initiate a USB remote wakeup.

An internal EEPROM controller exists to load various USB configuration information and the device MAC address. The

integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.

2.2.2

USB

The USB portion of LAN950x consists of the USB Device Controller (UDC), USB Bulk Out Packet Receiver (URX), USB

Bulk In Packet Transmitter (UTX), Control Block (CTL), System Control and Status Registers (SCSR), and USB PHY.

The USB device controller (UDC) contains a USB low-level protocol interpreter that controls the USB bus protocol,

packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding with autonomous error handling. It is

capable of operating either in USB 1.1 or 2.0 compliant modes. It has autonomous protocol handling functions like stall

condition clearing on setup packets, suspend/resume/reset conditions, and remote wakeup. It also autonomously han-

dles contingency operations for error conditions such as retry for CRC errors, Data toggle errors, and generation of

NYET, STALL, ACK and NACK depending on the endpoint buffer status. The UDC implements four USB endpoints:

Control, Interrupt, Bulk-In, and Bulk-Out.

The Control block (CTL) manages traffic to/from the control endpoint that is not handled by the UDC and constructs the

packets used by the interrupt endpoint. The CTL is responsible for handling some USB standard commands and all ven-

dor specific commands. The vendor specific commands allow for efficient statistics collection and access to the SCSR.

The URX and UTX implement the bulk-out and bulk-in pipes, respectively, which connect the USB Host and the UDC.

They perform the following functions:

The URX passes USB Bulk-Out packets to the FIFO Controller (FCT). It tracks whether or not a USB packet is errone-

ous. It instructs the FCT to flush erroneous packets by rewinding its write pointer.

The UTX retrieves Ethernet frames from the FCT and constructs USB Bulk-In packets from them. If the handshake for

a transmitted Bulk-In packet does not complete, the UTX is capable of retransmitting the packet. The UTX will not

instruct the FCT to advance its read head pointer until the current USB packet has been successfully transmitted to the

USB Host.

Both the URX and UTX are responsible for handling Ethernet frames encapsulated over USB by one of the following

methods.

• Multiple Ethernet frames per USB Bulk packet

• Single Ethernet frame per USB Bulk packet

The UDC also implements the System Control and Status Register (SCSR) space used by the Host to obtain status and

control overall system operation.

The integrated USB 2.0 compliant device PHY supports high speed and full speed modes.

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