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LAN9500AI Datasheet(PDF) 10 Page - Microchip Technology

Part # LAN9500AI
Description  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI Datasheet(HTML) 10 Page - Microchip Technology

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LAN950x
DS00001875A-page 10
 2010 - 2015 Microchip Technology Inc.
2.2.7
EEPROM CONTROLLER (EPC)
LAN950x contains an EEPROM controller for connection to an external EEPROM. This allows for the automatic loading
of static configuration data upon power-on reset, pin reset, or software reset. The EEPROM can be configured to load
USB descriptors, USB device configuration, and MAC address.
Custom operation without EEPROM is also provided via use of Descriptor RAM and Attributes Registers
(LAN9500A/LAN9500Ai ONLY).
2.2.8
GENERAL PURPOSE I/O
When configured for internal PHY mode, up to eleven GPIOs are supported. All GPIOs can serve as remote wakeup
events when the LAN950x is in a suspended state.
2.2.9
TAP CONTROLLER
IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.
2.2.10
CONTROL AND STATUS REGISTERS (CSR)
LAN950x’s functions are controlled and monitored by the Host via the Control and Status Registers (CSR). This register
space includes registers that control and monitor the USB controller, as well as elements of overall system operation
(System Control and Status Registers - SCSR), the MAC (MAC Control and Status Registers - MCSR), and the PHY
(accessed indirectly through the MAC via the MII_ACCESS and MII_DATA registers). The CSR may be accessed via
the USB Vendor Commands (REGISTER READ/REGISTER WRITE). Please refer to Section 5.3.3, "USB Vendor Com-
mands," on page 41 for more information.
2.2.11
RESETS
LAN950x supports the following system reset events:
• Power on Reset (POR)
• Hardware Reset Input Pin Reset (nRESET)
• Lite Reset (LRST)
• Software Reset (SRST)
• USB Reset
• VBUS Reset
The device supports the following module level reset events:
• Ethernet PHY Software Reset (PHY_RST)
• nTRST Pin Reset for Tap Controller
2.2.12
TEST FEATURES
Read/Write access to internal SRAMs is provided via the CSRs. JTAG based USB BIST is available. Full internal scan
and At Speed scan are supported.
2.2.13
SYSTEM SOFTWARE
LAN950x software drivers are available for the following operating systems:
• Windows XP
• Windows Vista
•Linux
•Win CE
•MAC OS
In addition, an EEPROM programming utility is available for configuring the external EEPROM.



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