LAN9500AI datasheet(103/213 Pages) MICROCHIP

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 2010 - 2015 Microchip Technology Inc.

DS00001875A-page 103

LAN950x

5.12.1.2

LAN9500A/LAN9500Ai Wake Detection Logic

A simplified diagram of the wake event detection logic for LAN9500A/LAN9500Ai is shown in Figure 5-33.

The functionality of GPIOs 0-6 and GPIOs 8-10 is slightly different. The functionality of GPIO7 is similar to that of GPIOs

0-6, with the additional requirement that it must cause a wakeup event when enabled for use in PHY Link Up detection.

GPIOs 8-10 are available for use in both internal and external PHY mode of operation. Their functionality is depicted in

Figure 5-36.

FIGURE 5-33:

WAKE EVENT DETECTION BLOCK DIAGRAM (LAN9500A/LAN9500AI)

Note:

Diagram does not represent actual hardware implementation.

Note:

GPIOs 0-7 are only available for use during internal PHY Mode of operation. The functionality of GPIOs 0-

6 is depicted in Figure 5-34, while that of GPIO7 is shown in Figure 5-35.

WOL_EN

(PMT_CTL Register)

WUPS[1]

(PMT_CTL Register)

SUSPEND0

ED_EN

(PMT_CTL Register)

WUPS[0]

(PMT_CTL Register)

WUEN

(WUSCR Register)

WUFR

(WUSCR Register)

MPEN

(WUSCR Register)

MPR

(WUSCR Register)

GPIO0_DET

GUEN

(WUSCR Register)

remote_wake

PFDA_EN

(WUSCR Register)

PFDA_FR

(WUSCR Register)

BCAST_EN

(WUSCR Register)

BCAST_FR

(WUCSR Register)

Good Frame

Received

SUSPEND1

SUSPEND2

SUSPEND3

WUFR

(WUSCR Register)

WUEN

(WUSCR Register)

GPIO10_DET

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