PCINT13 datasheet(57/294 Pages) ATMEL

57 / 294 page

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the

flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the reset can be found by examining the Reset Flags.

6.2

Internal Voltage Reference

The Atmel

® AVR® features an internal bandgap reference. This reference is used for

Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

6.2.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in Table 23-7 on page 259. To save power, the reference is not always

turned on. The reference is on during the following situations:

When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).

When the bandgap reference is connected to the Analog Comparator (by setting the

ACIRS bit in ACSR).

When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACIRS bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode or in Power-save, the user

can avoid the three conditions above to ensure that the reference is turned off before entering

in these power reduction modes.

6.3

Watchdog Timer

The Atmel AVR has an Enhanced Watchdog Timer (WDT). The main features are:

• Clocked from separate On-chip Oscillator

• 4 Operating modes

–Interrupt

– System Reset

– Interrupt and System Reset

– Clock Monitoring

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

6.3.1

Watchdog Timer Behavior

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 KHz

oscillator.

PCINT13 Datasheet(PDF) 57 Page - ATMEL Corporation

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