PCINT13 datasheet(12/294 Pages) ATMEL

12 / 294 page

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash Program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant

and a register. Single register operations can also be executed in the ALU. After an arithmetic

operation, the Status Register is updated to reflect information about the result of the

operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most Atmel® AVR® instructions have a single 16-bit

word format. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on

the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the

Stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-

grams must initialize the SP in the Reset routine (before subroutines or interrupts are

executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM

can easily be accessed through the five different addressing modes supported in the Atmel

AVR architecture.

The memory spaces in the Atmel AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector

position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F.

2.2

ALU – Arithmetic Logic Unit

The high-performance Atmel AVR ALU operates in direct connection with all the 32 general

purpose working registers. Within a single clock cycle, arithmetic operations between general

purpose registers or between a register and an immediate are executed. The ALU operations

are divided into three main categories – arithmetic, logical, and bit-functions. Some implemen-

tations of the architecture also provide a powerful multiplier supporting both signed/unsigned

multiplication and fractional format. See the “Instruction Set” section for a detailed description.

2.3

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using

the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and

restored when returning from an interrupt. This must be handled by software.

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