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R8C/13 Datasheet(PDF) 198 Page - Renesas Technology Corp |
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R8C/13 Datasheet(HTML) 198 Page - Renesas Technology Corp |
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198 / 224 page ![]() R8C/13 Group 19. Usage Notes Rev.1.20 Jan 27, 2006 page 187 of 205 REJ09B0111-0120 19. Usage Notes 19.1 Stop Mode and Wait Mode 19.1.1 Stop Mode When entering stop mode, set the CM10 bit to “1” (stop mode) after setting the FMR01 bit to “0” (CPU rewrite mode disabled). The instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1” (stop mode) and the program stops. Insert at least 4 NOP instruc- tions after inserting the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”. Use the next program to enter stop mode. • Program of entering stop mode BCLR 1, FMR0 ; CPU rewrite mode disabled BSET 0, PRCR ; Protect exited BSET 0, CM1 ; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP 19.1.2 Wait Mode When entering wait mode, execute the WAIT instruction after setting the FMR01 bit to “0” (CPU re- write mode disabled). The instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. Also, the value in the specific internal RAM area may be rewritten when exiting wait mode if writing to the interna RAM area before executing the WAIT instruction and entering wait mode. The area for a maximum of 3 bytes is rewirtten from the following address of the internal RAM in which the writing is performed before the WAIT instruction. If this causes a problem, avoid by inserting the JMP.B instruc- tion between the writing instruction to the internal RAM area and WAIT instruction as shown in the following program example. • Example to execute WAIT instruction Program Example MOV.B #055h,0601h ; Write to internal RAM area ••• JMP.B LABEL_001 LABEL_001 : FSET I ; Interrupt enabled BCLR 1,FMR0 ; CPU rewrite mode disabled WAIT ; Wait mode NOP NOP NOP NOP When accessing any area other than the internal RAM area between the writing instruction to the internal RAM area and execution of the WAIT instruction, this situation will not occur. |
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