R8CSLASH13 datasheet(126/224 Pages) RENESAS

126 / 224 page

Rev.1.20

Jan 27, 2006

page 115 of 205

REJ09B0111-0120

R8C/13 Group

13.1 Clock Synchronous Serial I/O Mode

Bit

Function

U0TB

0 to 7

Set transmission data

U0RB

0 to 7

Reception data can be read

OER

Overrun error flag

U0BRG

0 to 7

Set a bit rate

U0MR

SMD2 to SMD0

Set to “0012”

CKDIR

Select the internal clock or external clock

U0C0

CLK1 to CLK0

Select the count source for the U0BRG register

TXEPT

Transmit register empty flag

NCH

Select TxD0 pin output mode

CKPOL

Select the transfer clock polarity

UFORM

Select the LSB first or MSB first

U0C1

Set this bit to “1” to enable transmission/reception

Transmit buffer empty flag

Set this bit to “1” to enable reception

Reception complete flag

UCON

U0IRS

Select the source of UART0 transmit interrupt

U0RRM

Set this bit to “1” to use continuous receive mode

TXDISEL

Set to “0”

TXDIEN

Set to “0”

Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode

NOTES:

1. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock

synchronous serial I/O mode.

Table 13.3 lists the functions of the I/O pins during clock synchronous serial I/O mode. Note that for a

period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs an

“H”. (If the NCH bit is set to “1”(N-channel open-drain output), this pin is in high-impedance state.)

Table 13.3 Pin Functions

Pin name

Function

Method of selection

TxD0

(P14)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

(Outputs dummy data when performing reception only)

RxD0

(P15)

CLK0

(P16)

U0MR register CKDIR bit=0

U0MR register CKDIR bit=1

PD1 register PD1_6 bit=0

PD1 register PD1_5 bit=0

(P15 can be used as an input port when performing transmission only)

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