R8CSLASH13 datasheet(123/224 Pages) RENESAS

123 / 224 page

Rev.1.20

Jan 27, 2006

page 112 of 205

REJ09B0111-0120

R8C/13 Group

13. Serial Interface

UARTi transmit/receive mode register (i=0, 1)

SymbolAddressAfter reset

U0MR00A016

0016

U1MR00A816

0016

b7b6b5b4

b3b2b1b0

Bit name

Bit

symbol

CKDIR

SMD1

SMD0

Serial interface mode

select bit(2)

SMD2

Internal/external clock

select bit(3)

STPS

PRY

PRYE

(b7)

Parity enable bit

0 : Internal clock

1 : External clock(1)

Stop bit length select bit

Odd/even parity select bit

Reserved bit

0 : 1 stop bit

1 : 2 stop bits

0 : Parity disabled

1 : Parity enabled

0 0 0 : Serial interface disabled

0 0 1 : Clock synchronous serial I/O mode

1 0 0 : UART mode transfer data 7 bits long

1 0 1 : UART mode transfer data 8 bits long

1 1 0 : UART mode transfer data 9 bits long

Must not be set except above

b2 b1 b0

Effective when PRYE = 1

0 : Odd parity

1 : Even parity

Must set to “0”

Function

NOTES:

1. Must set the P1_6 bit in the PD1 register to “0” (input).

2. For the U1MR register, the SMD2 to SMD0 bits must not be set except the followings: “0002”, “1002”, “1012”, or “1102”.

3. Must set the CKDIR bit to “0” (internal clock) in UART1.

UARTi transmit/receive control register 0 (i=0, 1)

SymbolAddressAfter reset

U0C000A416

0816

U1C000AC16

0816

Function

TXEPT

CLK1

CLK0

(b2)

NCH

CKPOL

BRG count source

select bit(1)

Transmit register empty

flag

0 : Transmit data is output at falling edge of transfer clock

and receive data is input at rising edge

1 : Transmit data is output at rising edge of transfer clock

and receive data is input at falling edge

CLK polarity select bit

Data output select bit

0 0 : f1SIO is selected

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Avoid this setting

b1 b0

0 : LSB first

1 : MSB first

0 : Data present in transmit register (during transmission)

1 : No data present in transmit register

(transmission completed)

Nothing is assigned.

When write, set to “0”. When read, its content is indeterminate.

0 : TxDi pin is a pin of CMOS output

1 : TxDi pin is a pin of N-channel open-drain output

UFORMTransfer format select bit

Bit name

Bit

symbol

Reserved bitSet to “0”

(b4)

NOTES:

1. If the BRG count source is switched, set the UiBRG register again.

Figure 13.4 U0MR and U1MR Registers and U0C0 and U1C0 Registers

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