R8CSLASH13 datasheet(118/224 Pages) RENESAS

118 / 224 page

Rev.1.20

Jan 27, 2006

page 107 of 205

REJ09B0111-0120

R8C/13 Group

12.4 Timer (Timer C)

12.4.2 Output Compare Mode

In this mode, an interrupt request is generated when the value of TC register matches the value of

TM0 or TM1 register. Table 12.14 shows specifications in output compare mode. Figure 12.34 shows

an operation example of output compare mode.

Item

Specification

Count source

f1, f8, f32, fRING-fast

Count operation

• Count up

• Value in TC register is set to “000016” when a counting stops

Count start condition

TCC00 bit in TCC0 register is set to “1” (count start)

Count stop condition

TCC00 bit in TCC0 register is set to “0” (count stop)

Waveform output start

When “1” (CMP output enabled) is written to TCOUT0 to TCOUT5 bits.(2)

condition

Waveform output stop

When “0” (CMP output disabled) is written to TCOUT0 to TCOUT5 bits.

condition

Interrupt request

• When a match occurs in compare circuit 0 [compare 0 interrupt]

generation timing

• When a match occurs in compare circuit 1 [compare 1 interrupt]

• When Time C overflows [Timer C interrupt]

______

INT3/TCIN pin function

_______

Programmable I/O port or INT3 interrupt input

P10 to P12 pins and P30 to Programmable I/O port or CMP output(2)

P32 pins function

Counter value reset timing

When TCC00 bit in TCC0 register is set to “0” (count stop)

Read from timer(1)

• Value in compare register can be read out by reading TM0 register and TM1 register.

• Count value can be read out by reading TC register.

Write to timer(1)

• Write to TC register is disabled.

• Values written to TM0 register and TM1 register are stored in compare register at the

following timings:

- When TM0 and TM1 registers are written if TCC00 bit is “0” (count stop)

- When counter overflows if TCC00 bit is “1” (in counting) and TCC12 bit in TCC1

- When compare 1 matches counter if TCC00 bit is “1” and TCC12 bit is “1” (set TC

Select function

• Timer C counter reload select function

Counter value in TC register at match occurrence in compare circuit 1 is set or not set

to “000016” selected by TCC12 bit in TCC1 register.

• Output level at match occurrence in compare circuit 0 can be selected by TCC15 to

TCC14 bits in TCC1 register. Similarly, output level at match occurrence in compare

circuit 1 can be selected by TCC17 to TCC16 bits in TCC1 register.

• Whether output is reversed or not can be selected by TCOUT1 to TCOUT0 bits in

TCOUT register.

NOTES:

1. TC, TM0, and TM1 registers should be accessed in 16-bit units.

2. When the corresponding port data is “1”, the waveform is output depending on the setting of the registers TCC1 and

TCOUT. When the corresponding port data is “0”, the fixed level is output (refer to Figure 12.30 CMP Waveform

Output Unit.

Table 12.14 Output Compare Mode Specifications

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