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R8C/13 Datasheet(PDF) 116 Page - Renesas Technology Corp |
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R8C/13 Datasheet(HTML) 116 Page - Renesas Technology Corp |
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116 / 224 page ![]() Rev.1.20 Jan 27, 2006 page 105 of 205 REJ09B0111-0120 R8C/13 Group 12.4 Timer (Timer C) 12.4.1 Input Capture Mode This mode uses an edge input to TCIN pin or the fRING128 clock as trigger to latch the timer value and generates an interrupt request. The TCIN input has a digital filter and this prevents an error caused by noise or so on from occurring. Table 12.13 shows specifications in input capture mode. Figure 12.33 shows an operation example of input capture mode. Item Specification Count source f1, f8, f32, fRING-fast Count operation • Count up • Transfer value in TC register to TM0 register at active edge of measurement pulse • Value in TC register is set to “000016” when a counting stops Count start condition TCC00 bit in TCC0 register is set to “1” (count start) Count stop condition TCC00 bit in TCC0 register is set to “0” (count stop) Interrupt request _____ • When active edge of measurement pulse is input [INT3 interrupt](2) generation timing • When Timer C overflows [Timer C interrupt] ______ INT3/TCIN pin function _______ Programmable I/O port or measurement pulse input (INT3 interrupt input) P10 to P12, P33 to P35 Programmable I/O port pin function Counter value reset timing When TCC00 bit in TCC0 register is set to “0” (capture disabled) Read from timer(1) • Count value can be read out by reading TC register. • Count value at measurement pulse active edge input can be read out by reading TM0 register. Write to timer Write to TC register and TM0 register is disabled Select function _____ • INT3/TCIN polarity select function Measurement pulse active edge is selected by TCC03 to TCC04 bits • Digital filter function Digital filter sampling frequency is selected by TCC11 to TCC10 bits • Trigger select function TCIN input or fRING128 is selected by TCC07 bit. NOTES: 1. TC register and TM0 register must be read in 16-bit units. _______ 2. The INT3 interrupt is acknowledged by digital filter delay and one count source cycle delay (max.) Table 12.13 Input Capture Mode Specifications |
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