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R8C/13 Datasheet(PDF) 115 Page - Renesas Technology Corp |
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R8C/13 Datasheet(HTML) 115 Page - Renesas Technology Corp |
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115 / 224 page  Rev.1.20 Jan 27, 2006 page 104 of 205 REJ09B0111-0120 R8C/13 Group 12.4 Timer (Timer C) Figure 12.32 TCC1 Register and TCOUT Register Timer C control register 1 SymbolAddressAfter reset TCC1009B16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 TCC11 TCC10 b1 b0 INT3 input filter select bit(1) Timer C counter reload select bit(3) TCC12 RW RW RW RW 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling 0: No reload (free-run) 1: Set TC register to “000016” at compare 1 match NOTES: 1. Input is recognized only when the same value from INT3 pin is sampled three times in succession. 2. The TCC00 bit in the TCC0 register should be set to “0” (count stop) when rewriting the TCC13 bit. 3. The TCC12 and TCC14 to TCC17 should be set to “0” when the TCC13 bit is “0” (input capture mode). Compare 0/Capture select bit(2) TCC13 RW 0: Capture (input capture mode)(3) 1: Compare 0 output (output compare mode) Compare 0 output mode select bit(3) TCC14 RW 0 0: CMP output remains unchanged even when compare 0 signal matched 0 1: CMP output is reversed when compare 0 signal is matched 1 0: CMP output is set to low when compare 0 signal is matched 1 1: CMP output is set to high when compare 0 signal is matched b5 b4 Compare 1 output mode select bit(3) TCC16 RW 0 0: CMP output remains unchanged even when compare 1 signal matched 0 1: CMP output is reversed when compare 1 signal is matched 1 0: CMP output is set to low when compare 1 signal is matched 1 1: CMP output is set to high when compare 1 signal is matched b7 b6 TCC15 TCC17 Timer C output control register Symbol Address After reset TCOUT 00FF16 0016 Bit name Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 TCOUT1 TCOUT0 CMP output enable bit 0 RW RW RW 0: Disable CMP output from CMP00 1: Enable CMP output from CMP00 NOTES: 1. Set the bits which are not used for the CMP output to “0”. CMP output enable bit 2 TCOUT4 RW TCOUT6 RW TCOUT5 CMP output enable bit 1 0: Disabe CMP output from CMP01 1: Enable CMP output from CMP01 0: Disable CMP output from CMP02 1: Enable CMP output from CMP02 CMP output reverse bit 0 0: Not reverse CMP output from CMP10 to CMP12 1: Reverse CMP output from CMP10 to CMP12 CMP output reverse bit 1 RW TCOUT2 RW TCOUT3 CMP output enable bit 3 0: Disable CMP output from CMP10 1: Enable CMP output from CMP10 RW CMP output enable bit 4 0: Disable CMP output from CMP11 1: Enable CMP output from CMP11 CMP output enable bit 5 0: Disable CMP output from CMP12 1: Enable CMP output from CMP12 RW 0: Not reverse CMP output from CMP00 to CMP02 1: Reverse CMP output from CMP 00 to CMP02 TCOUT7 (1) |
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