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HD6432138SW Datasheet(PDF) 592 Page - Renesas Technology Corp

Part # HD6432138SW
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1061 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 592 Page - Renesas Technology Corp

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Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 538 of 1004
REJ09B0301-0400
only when register IDR1 is accessed using
CS1. Slave logic decodes the commands input from the
host processor. When an H'D1 host command is detected, bit 1 of the data following the host
command is output from the GA20 output pin. This operation does not depend on firmware or
interrupts, and is faster than the regular processing using interrupts. Table 17.7 lists the conditions
that set and clear GA20 (P81). Figure 17.2 shows the GA20 output in flowchart form. Table 17.8
indicates the GA20 output signal values.
Table 17.7
GA20 (P81) Set/Clear Timing
Pin Name
Setting Condition
Clearing Condition
GA20 (P81) Rising edge of the host’s write signal
(
IOW) when bit 1 of the written data is 1
and the data follows an H'D1 host
command
Rising edge of the host’s write signal
(
IOW) when bit 1 of the written data is 0
and the data follows an H'D1 host
command
Also, when bit FGA20E in HICR is cleared
to 0
Start
Host write
H'D1 command
received?
Wait for next byte
Host write
Yes
Data byte?
Write bit 1 of data byte
to DR bit of P81/GA20
Yes
No
No
Figure 17.2 GA20 Output



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