HD6432138SW datasheet(589/1061 Pages) RENESAS

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 535 of 1004

REJ09B0301-0400

Table 17.4

Set/Clear Timing for STR2 Flags

Flag

Setting Condition

Clearing Condition

Rising edge of host’s write signal

(

IOW) when HA0 is high

Rising edge of host’s write signal (

IOW) when

HA0 is low

IBF*

Rising edge of host’s write signal

(

IOW) when writing to IDR2

Falling edge of slave’s internal read signal

(

RD) when reading IDR2

OBF

Falling edge of slave’s internal write

signal (

WR) when writing to ODR2

Rising edge of host’s read signal (

IOR) when

reading ODR2

Note:

The IBF flag setting and clearing conditions are different when the fast A20 gate is

used. For details see table 17.8, Fast A20 Gate Output Signals.

17.2.10

Module Stop Control Register (MSTPCR)

MSTP15

R/W

Bit

Initial value

Read/Write

MSTP14

R/W

MSTP13

R/W

MSTP12

R/W

MSTP11

R/W

MSTP10

R/W

MSTP9

R/W

MSTP8

R/W

MSTP7

R/W

MSTP6

R/W

MSTP5

R/W

MSTP4

R/W

MSTP3

R/W

MSTP2

R/W

MSTP1

R/W

MSTP0

R/W

MSTPCRH

MSTPCRL

MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.

When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section

24.5, Module Stop Mode, for details.

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.

MSTPCRL

Bit 2

MSTP2

Description

Host interface module stop mode is cleared

Host interface module stop mode is set

(Initial value)

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