HD6432138SW datasheet(591/1061 Pages) RENESAS

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 537 of 1004

REJ09B0301-0400

Table 17.6

Host Interface Operation

CS2

CS1

IOR

IOW

HA0

Operation

Setting prohibited

Data read from output data register 1 (ODR1)

Status read from status register 1 (STR1)

Data write to input data register 1 (IDR1)

Command write to input data register 1 (IDR1)

Idle state

Setting prohibited

Data read from output data register 2 (ODR2)

Status read from status register 2 (STR2)

Data write to input data register 2 (IDR2)

Command write to input data register 2 (IDR2)

Idle state

17.3.3

A20 Gate

The A20 gate signal can mask address A20 to emulate an addressing mode used by personal

computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be

output under firmware control, or a fast A20 gate signal can be output under hardware control.

Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0).

Note: *

Intel microprocessor.

Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1

command followed by data. When the slave processor receives data, it normally uses an interrupt

routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command,

software copies bit 1 of the data and outputs it at the gate A20 pin.

Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a

fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. The initial output

from this pin will be a logic 1, which is the initial value. Afterward, the host processor can

manipulate the output from this pin by sending commands and data. This function is available

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