HD6432138SW datasheet(595/1061 Pages) RENESAS

595 / 1061 page

Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 541 of 1004

REJ09B0301-0400

17.4

Interrupts

17.4.1

IBF1, IBF2

The host interface can issue two interrupt requests to the slave CPU: IBF1 and IBF2. They are

input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is

enabled when the corresponding enable bit is set.

Table 17.10 Input Buffer Full Interrupts

Interrupt

Description

IBF1

Requested when IBFIE1 is set to 1 and IDR1 is full

IBF2

Requested when IBFIE2 is set to 1 and IDR2 is full

17.4.2

HIRQ11, HIRQ1, and HIRQ12

In slave mode (single-chip mode, with HI12E = 1 in SYSCR2), bits P45DR to P43DR in the port

4 data register (P4DR) can be used as host interrupt request latches.

These three P4DR bits are cleared to 0 by the host processor’s read signal (

IOR). If CS1 and HA0

are low, when

IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If

CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To

generate a host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In

processing the interrupt, the host’s interrupt handling routine reads the output data register (ODR1

or ODR2), and this clears the host interrupt latch to 0.

Table 17.11 indicates how these bits are set and cleared. Figure 17.3 shows the processing in

flowchart form.

Table 17.11 HIRQ Setting/Clearing Conditions

Host Interrupt

Signal

Setting Condition

Clearing Condition

HIRQ11 (P43)

Slave CPU reads 0 from bit P43DR,

then writes 1

Slave CPU writes 0 in bit P43DR, or

host reads output data register 2

HIRQ1 (P44)

Slave CPU reads 0 from bit P44DR,

then writes 1

Slave CPU writes 0 in bit P44DR, or

host reads output data register 1

HIRQ12 (P45)

Slave CPU reads 0 from bit P45DR,

then writes 1

Slave CPU writes 0 in bit P45DR, or

host reads output data register 1

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