HD6432138SW datasheet(27/1061 Pages) RENESAS

27 / 1061 page

Rev. 4.00 Jun 06, 2006 page xxvii of liv

16.1.3 Input/Output Pins ................................................................................................. 458

16.1.4 Register Configuration......................................................................................... 459

16.2

Register Descriptions ........................................................................................................ 460

16.2.1 I

2C Bus Data Register (ICDR) ............................................................................. 460

16.2.2 Slave Address Register (SAR) ............................................................................. 463

16.2.3 Second Slave Address Register (SARX) ............................................................. 464

16.2.4 I

2C Bus Mode Register (ICMR) ........................................................................... 465

16.2.5 I

2C Bus Control Register (ICCR) ......................................................................... 468

16.2.6 I

2C Bus Status Register (ICSR)............................................................................ 475

16.2.7 Serial Timer Control Register (STCR) ................................................................ 480

16.2.8 DDC Switch Register (DDCSWR) ...................................................................... 481

16.2.9 Module Stop Control Register (MSTPCR) .......................................................... 484

16.3

Operation .......................................................................................................................... 485

16.3.1 I

2C Bus Data Format ............................................................................................ 485

16.3.2 Master Transmit Operation .................................................................................. 487

16.3.3 Master Receive Operation.................................................................................... 489

16.3.4 Slave Receive Operation...................................................................................... 492

16.3.5 Slave Transmit Operation .................................................................................... 495

16.3.6 IRIC Setting Timing and SCL Control ................................................................ 496

16.3.7 Automatic Switching from Formatless Mode to I

2C Bus Format ........................ 498

16.3.8 Operation Using the DTC .................................................................................... 499

16.3.9 Noise Canceler ..................................................................................................... 500

16.3.10 Sample Flowcharts............................................................................................... 500

16.3.11 Initialization of Internal State .............................................................................. 505

16.4

Usage Notes ...................................................................................................................... 506

Section 17 Host Interface [H8S/2138 Group] ............................................................. 523

17.1

Overview........................................................................................................................... 523

17.1.1 Features................................................................................................................ 523

17.1.2 Block Diagram ..................................................................................................... 524

17.1.3 Input and Output Pins .......................................................................................... 525

17.1.4 Register Configuration......................................................................................... 526

17.2

Register Descriptions ........................................................................................................ 527

17.2.1 System Control Register (SYSCR) ...................................................................... 527

17.2.2 System Control Register 2 (SYSCR2) ................................................................. 528

17.2.3 Host Interface Control Register (HICR) .............................................................. 529

17.2.4 Input Data Register 1 (IDR1)............................................................................... 530

17.2.5 Output Data Register 1 (ODR1)........................................................................... 530

17.2.6 Status Register 1 (STR1) ..................................................................................... 531

17.2.7 Input Data Register 2 (IDR2)............................................................................... 532

17.2.8 Output Data Register 2 (ODR2)........................................................................... 533

HD6432138SW Datasheet(PDF) 27 Page - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 27 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL