HD6432138SW datasheet(596/1061 Pages) RENESAS

596 / 1061 page

Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 542 of 1004

REJ09B0301-0400

Slave CPU

Master CPU

Write to ODR

Write 1 to P4DR

P4DR = 0?

Yes

All bytes

transferred?

HIRQ output high

HIRQ output low

Interrupt initiation

ODR read

Hardware operations

Software operations

Figure 17.3 HIRQ Output Flowchart

HIRQ Setting/Clearing Contention: If there is contention between a P4DR read/write by the

CPU and P4DR (HIRQ11, HIRQ1, HIRQ12) clearing by the host, clearing by the host is held

pending during the P4DR read/write by the CPU. P4DR clearing is executed after completion of

the read/write.

17.5

Usage Note

The host interface provides buffering of asynchronous data from the host and slave processors, but

an interface protocol must be followed to implement necessary functions and avoid data

contention. For example, if the host and slave processors try to access the same input or output

data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple

and effective protocol.

Also, if

CS1 and CS2 or ECS2 are driven low simultaneously in attempting IDR or ODR access,

signal contention will occur within the chip, and a through-current may result. This usage must

therefore be avoided.

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