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HD6432138SW Datasheet(PDF) 588 Page - Renesas Technology Corp

Part # HD6432138SW
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1061 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 588 Page - Renesas Technology Corp

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Section 17 Host Interface [H8S/2138 Group]
Rev. 4.00 Jun 06, 2006 page 534 of 1004
REJ09B0301-0400
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR2.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 17.8, Fast A20 Gate Output Signals.
Bit 1
IBF
Description
0
[Clearing condition]
When the slave processor reads IDR2
(Initial value)
1
[Setting condition]
When the host processor writes to IDR2
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to
0 when the host processor reads ODR2. The IBF flag setting and clearing conditions are different
when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals.
Bit 0
OBF
Description
0
[Clearing condition]
When the host processor reads ODR2 or the slave writes 0 in the OBF bit
(Initial value)
1
[Setting condition]
When the slave processor writes to ODR2
Table 17.4 shows the conditions for setting and clearing the STR2 flags.



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