HD6432138SW datasheet(586/1061 Pages) RENESAS

586 / 1061 page

Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 532 of 1004

REJ09B0301-0400

Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to

0 when the host processor reads ODR1.

Bit 0

OBF

Description

[Clearing condition]

When the host processor reads ODR1 or the slave writes 0 in the OBF bit

(Initial value)

[Setting condition]

When the slave processor writes to ODR1

Table 17.3 shows the conditions for setting and clearing the STR1 flags.

Table 17.3

Set/Clear Timing for STR1 Flags

Flag

Setting Condition

Clearing Condition

Rising edge of host’s write signal

(

IOW) when HA0 is high

Rising edge of host’s write signal (

IOW) when

HA0 is low

IBF*

Rising edge of host’s write signal

(

IOW) when writing to IDR1

Falling edge of slave’s internal read signal

(

RD) when reading IDR1

OBF

Falling edge of slave’s internal write

signal (

WR) when writing to ODR1

Rising edge of host’s read signal (

IOR) when

reading ODR1

Note:

The IBF flag setting and clearing conditions are different when the fast A20 gate is

used. For details see table 17.8, Fast A20 Gate Output Signals.

17.2.7

Input Data Register 2 (IDR2)

Bit

Initial value

Slave Read/Write

Host Read/Write

IDR7

—

IDR6

—

IDR5

—

IDR4

—

IDR3

—

IDR0

—

IDR2

—

IDR1

—

IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the

host processor. When

CS2 is low, information on the host data bus is written into IDR2 at the

rising edge of

IOW. The HA0 state is also latched into the C/D bit in STR2 to indicate whether the

written information is a command or data.

The initial values of IDR2 after a reset and in standby mode are undetermined.

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