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HD6432138SW Datasheet(PDF) 582 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 582 Page - Renesas Technology Corp |
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582 / 1061 page ![]() Section 17 Host Interface [H8S/2138 Group] Rev. 4.00 Jun 06, 2006 page 528 of 1004 REJ09B0301-0400 17.2.2 System Control Register 2 (SYSCR2) Bit 7 654 321 0 KWUL1 KWUL0 P6PUE — SDE CS4E CS3E HI12E Initial value 0 000 000 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface functions are enabled or disabled by the HI12E bit in SYSCR2. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be set and changed by software. For details see section 8, I/O Ports. Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see section 8, I/O Ports. Bit 4—Reserved: Do not write 1 to this bit. Bit 3—Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function. When this function is enabled, host interface pin functions can be halted, and the pins placed in the high-impedance state, according to the state of the HIFSD pin. Bit 3 SDE Description 0 Host interface pin shutdown function disabled (Initial value) 1 Host interface pin shutdown function enabled Bit 2—CS4 Enable (CS4E): Reserved. Do not write 1 to this bit. Bit 1—CS3 Enable (CS3E): Reserved. Do not write 1 to this bit. Bit 0—Host Interface Enable Bit (HI12E): Enables or disables host interface functions in single-chip mode. When the host interface functions are enabled, slave mode is entered and processing is performed for data transfer between the slave and host. |
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