HD6432138SW datasheet(581/1061 Pages) RENESAS

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 527 of 1004

REJ09B0301-0400

17.2

17.2.1

System Control Register (SYSCR)

Bit

Initial value

Read/Write

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

SYSCR is an 8-bit readable/writable register which controls H8S/2138 Group chip operations. Of

the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be

accessed when the HIE bit is set to 1. The host interface

CS2 and ECS2 pins are controlled by the

CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System Control Register

(SYSCR), and section 5.2.1, System Control Register (SYSCR), for information on other SYSCR

bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode.

Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin

that performs the

CS2 function.

SYSCR

Bit 7

HICR

Bit 0

CS2E

FGA20E

Description

CS2 pin function halted (CS2 fixed high internally)

(Initial value)

CS2 pin function selected for P81/CS2 pin

CS2 pin function selected for P90/ECS2 pin

Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to the host interface

registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2,

and STR2) can be accessed.

Bit 1

HIE

Description

Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU

access is disabled

(Initial value)

Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU

access is enabled

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