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HD6432138SW Datasheet(PDF) 577 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 577 Page - Renesas Technology Corp |
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577 / 1061 page  Section 17 Host Interface [H8S/2138 Group] Rev. 4.00 Jun 06, 2006 page 523 of 1004 REJ09B0301-0400 Section 17 Host Interface [H8S/2138 Group] Provided in the H8S/2138 Group; not provided in the H8S/2134 Group. 17.1 Overview The H8S/2138 Group has an on-chip host interface (HIF) that enables connection to an ISA bus, widely used as the internal bus in personal computers. The host interface provides a dual-channel parallel interface between the on-chip CPU and a host processor. The host interface is available only when the HI12E bit is set to 1 in SYSCR2. This mode is called slave mode, because it is designed for a master-slave communication system in which the H8S/2138 Group chip is slaved to a host processor. 17.1.1 Features The features of the host interface are summarized below. The host interface consists of 4-byte data registers, 2-byte status registers, a 1-byte control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via five control signals from the host processor ( CS1, CS2 or ECS2, HA0, IOR, and IOW), four output signals to the host processor (GA20, HIRQ1, HIRQ11, and HIRQ12), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The CS1 and CS2 (or ECS2) signals select one of the two interface channels. |
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