HD6432138SW datasheet(584/1061 Pages) RENESAS

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 530 of 1004

REJ09B0301-0400

Bit 0—Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When

the fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using

firmware to manipulate the P81 output.

Bit 0

FGA20E

Description

Fast A20 gate function is disabled

(Initial value)

Fast A20 gate function is enabled

17.2.4

Input Data Register 1 (IDR1)

Bit

Initial value

Slave Read/Write

Host Read/Write

IDR7

—

IDR6

—

IDR5

—

IDR4

—

IDR3

—

IDR0

—

IDR2

—

IDR1

—

IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the

host processor. When

CS1 is low, information on the host data bus is written into IDR1 at the

rising edge of

IOW. The HA0 state is also latched into the C/D bit in STR1 to indicate whether the

written information is a command or data.

The initial values of IDR1 after a reset and in standby mode are undetermined.

17.2.5

Output Data Register 1 (ODR1)

Bit

Initial value

Slave Read/Write

Host Read/Write

ODR7

—

R/W

ODR6

—

R/W

ODR5

—

R/W

ODR4

—

R/W

ODR3

—

R/W

ODR0

—

R/W

ODR2

—

R/W

ODR1

—

R/W

ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register

to the host processor. The ODR1 contents are output on the host data bus when HA0 is low,

CS1

is low, and

IOR is low.

The initial values of ODR1 after a reset and in standby mode are undetermined.

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