HD6432138SW datasheet(587/1061 Pages) RENESAS

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 533 of 1004

REJ09B0301-0400

17.2.8

Output Data Register 2 (ODR2)

Bit

Initial value

Slave Read/Write

Host Read/Write

ODR7

—

R/W

ODR6

—

R/W

ODR5

—

R/W

ODR4

—

R/W

ODR3

—

R/W

ODR0

—

R/W

ODR2

—

R/W

ODR1

—

R/W

ODR2 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register

to the host processor. The ODR2 contents are output on the host data bus when HA0 is low,

CS2

is low, and

IOR is low.

The initial values of ODR2 after a reset and in standby mode are undetermined.

17.2.9

Status Register 2 (STR2)

Bit

Initial value

Slave Read/Write

Host Read/Write

Note: * Only 0 can be written, to clear the flag.

DBU

R/W

DBU

R/W

DBU

R/W

DBU

R/W

OBF

R/(W)*

DBU

R/W

IBF

STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3,

1, and 0 are read-only bits to both the host and slave processors.

STR2 is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.

Bit 3—Command/Data (C/

D): Receives the HA0 input when the host processor writes to IDR2,

and indicates whether IDR2 contains data or a command.

Bit 3

Description

Contents of input data register (IDR2) are data

(Initial value)

Contents of input data register (IDR2) are a command

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