HD6432138SW datasheet(583/1061 Pages) RENESAS

583 / 1061 page

Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 529 of 1004

REJ09B0301-0400

Bit 0

HI12E

Description

Host interface functions are disabled

(Initial value)

Host interface functions are enabled

17.2.3

Host Interface Control Register (HICR)

Bit

Initial value

Slave Read/Write

Host Read/Write

—

FGA20E

R/W

—

IBFIE2

R/W

—

IBFIE1

R/W

—

HICR is an 8-bit readable/writable register which controls host interface interrupts and the fast

A20 gate function. HICR is initialized to H'F8 by a reset and in hardware standby mode.

Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.

Bit 2—Input Data Register Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2

interrupt to the internal CPU.

Bit 2

IBFIE2

Description

Input data register (IDR2) receive complete interrupt is disabled

(Initial value)

Input data register (IDR2) receive complete interrupt is enabled

Bit 1— Input Data Register Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1

interrupt to the internal CPU.

Bit 1

IBFIE1

Description

Input data register (IDR1) receive complete interrupt is disabled

(Initial value)

Input data register (IDR1) receive complete interrupt is enabled

HD6432138SW Datasheet(PDF) 583 Page - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 583 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL