R8CSLASH20 datasheet(215/501 Pages) RENESAS

215 / 501 page

R8C/20 Group, R8C/21 Group

14. Timers

Rev.2.00 Aug 27, 2008

Page 199 of 458

REJ09B0250-0200

Figure 14.62 lists the Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi

Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin.

Figure 14.62

Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi

Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin

Set to 0 by a program

Value in TRDi register

Count source

TRDIOAi output

FFFFh

TRDIOBi output

m: Setting Value in TRDGRAi register

n: Setting Value in TRDGRCi register

p: Setting Value in TRDGRBi register

q: Setting Value in TRDGRDi register

The above applies to the following conditions:

The CSELi bit in the TRDSTR register is set to 1. (The TRDi register is not stopped by the compare match.)

The BFCi and BFDi bits in the TRDMR register are set to 0. (The TRDGRCi and TRDGRDi registers are not used as the buffer register.)

The EAi and EBi bits in the TRDOER1 register are set to 0. (Enable TRDIOAi and TRDIOBi pin outputs.)

The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b. (Set the TRDi register to 0000h by the compare match in the TRDGRAi register.)

The TOAi and TOBi bits in the TRDOCR register are set to 0. (initial output “L” to the compare match.)

The IOA2 to IOA0 bits in the TRDIORAi register are set to 011b. (TRDIOAi output inversed at the TRDGRAi register compare match.)

The IOB2 to IOB0 bits in the TRDIORAi register are set to 011b. (TRDIOBi output inversed at the TRDGRBi register compare match.)

The IOC3 to IOC0 bits in the TRDIORCi register are set to 0011b. (TRDIOAi output inversed at the TRDGRCi register compare match.)

The IOD3 to IOD0 bits in the TRDIORCi register are set to 0011b. (TRDIOBi output inversed at the TRDGRDi register compare match.)

i = 0 or 1

m + 1

n + 1

0000h

m - n

p + 1

p - q

q + 1

IMFA bit in

TRDSRi register

IMFC bit in

TRDSRi register

Set to 0 by a program

Output inversed by compare match

Initial output “L”

IMFB bit in

TRDSRi register

IMFD bit in

TRDSRi register

Initial output “L”

Set to 0 by a program

Output inversed by compare match

R8C/20 Datasheet(PDF) 215 Page - Renesas Technology Corp

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