R8CSLASH20 datasheet(152/501 Pages) RENESAS

152 / 501 page

R8C/20 Group, R8C/21 Group

14. Timers

Rev.2.00 Aug 27, 2008

Page 136 of 458

REJ09B0250-0200

14.1.6

Notes on Timer RA

• Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count

starts.

• Even if the prescaler and timer RA is read out in 16-bit units, these registers are read by 1 byte in the MCU.

Consequently, the timer value may be updated during the period these two registers are being read.

• In pulse width measurement mode and pulse period measurement mode, the TEDGF and TUNDF bits in

the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain

unchanged when 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR

executed. At the time, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the

MOV instruction.

• When changing to pulse width measurement mode and pulse period measurement mode from other mode,

the contents of the TEDGF and TUNDF bits are indeterminate. Write 0 to the TEDGF and TUNDF bits

before the count starts.

• The TEDGF bit may be set to 1 by timer RA prescaler underflow which is generated for the first time since

the count starts.

• When using the pulse period measurement mode, leave two periods or more of timer RA prescaler

immediately after count starts, and set the TEDGF bit to 0.

• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1

(count starts) while the count stops.

During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA

starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).

The TCSTF bit retains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops)

while the count is performing. Timer RA counting is stopped when the TCSTF bit is set to 0.

During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.

NOTE:

1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, TRA

• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow

three or more cycles of the count source clock for each write interval.

• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three

or more cycles of the prescaler underflow for each write interval.

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