R8CSLASH20 datasheet(115/501 Pages) RENESAS

115 / 501 page

R8C/20 Group, R8C/21 Group

12. Interrupts

Rev.2.00 Aug 27, 2008

Page 99 of 458

REJ09B0250-0200

12.1.6.8

Returning from an Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have

been saved to the stack, are automatically returned. The program, executed before the interrupt request has

been acknowledged, starts running again.

Return the register saved by a program in an interrupt routine using the POPM instruction or others before the

REIT instruction.

12.1.6.9

Interrupt Priority

If two or more interrupt requests are generated while executing one instruction, the interrupt with the higher

priority is acknowledged.

Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral functions).

However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by

hardware, with the higher priority interrupt acknowledged in hardware.

The priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set

by hardware.

Figure 12.10 shows the Priority Levels of Hardware Interrupts.

The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the

instruction is executed.

Figure 12.10

Priority Levels of Hardware Interrupts

Reset

Watchdog timer

Oscillation stop detection

Voltage monitor 2

Peripheral function

Single step

Address match

High

Low

Address break

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