R8CSLASH20 datasheet(456/501 Pages) RENESAS

456 / 501 page

R8C/20 Group, R8C/21 Group

21. Usage Notes

Rev.2.00 Aug 27, 2008

Page 440 of 458

REJ09B0250-0200

• The TRD1 register counts the order of 1, 0, FFFFh, 0, 1 when changing from decrement to increment.

The UDF bit is set to 1 by the order of 1, 0, FFFFh operation. Also, when the CMD1 to CMD0 bits in the

TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred by the underflow in

the TRD1 register), the content in the buffer register (TRDGRD0, TRDGRC1, TRDGRD1) is transferred

to the general register (TRDGRB0, TRDGRA1, TRDGRB1). For the order of FFFFh, 0, 1 operation, data

are not transferred to the register such as the TRDGRB0 register. Also, at this time, the OVF bit remains

unchanged.

Figure 21.5

Operation When TRD1 Register Underflows in Complementary PWM Mode

No change

UDF bit in

TRDSR0 register

Transferred from

buffer register

TRDGRB0 register

TRDGRA1 register

TRDGRB1 register

Count value in TRD0

Set to 0 by a program

Not transferred from buffer register

When the CMD1 to CMD0 bits in the

TRDFCR register are set to 10b.

(Transfer from the buffer register to the

general register when the TRD1 register

underflows)

OVF bit in

TRDSR0 register

FFFFh

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