R8CSLASH20 datasheet(357/501 Pages) RENESAS

357 / 501 page

R8C/20 Group, R8C/21 Group

16. Clock Synchronous Serial Interface

Rev.2.00 Aug 27, 2008

Page 341 of 458

REJ09B0250-0200

Figure 16.47

Example of Register Setting in Master Receive Mode (I2C Bus Interface Mode)

End

RDRF = 1 ?

Master receive mode

Yes

(1) Set the TEND bit to 0 and set to master receive mode.

Set the TDRE bit to 0(1,2)

(2) Set the ACKBT bit to the transmit device(1)

(3) Dummy-read to the ICDRR register(1)

(4) Wait for 1 byte to be received

(5) Judge (last receive - 1)

(6) Read the receive data

(7) Set the ACKBT bit of the last byte and set to disable the

continuous receive (RCVD = 1)(2)

(8) Read the receive data of (last byte - 1)

(9) Wait the last byte is received

(10) Set the STOP bit to 0

(11) Generate the stop condition

(12) Wait the stop condition is generated

(13) Read the receive data of the last byte

(14) Set the RCVD bit to 0

(15) Set to slave receive mode

ICCR1 register

TRS bit

← 0

Dummy-read in ICDRR register

Read RDRF bit in ICSR register

Last receive

- 1 ?

ICSR register

TEND bit

← 0

ICSR register

STOP bit

← 0

ICCR2 register

SCP bit

← 0

BBSY bit

← 0

Read STOP bit in ICSR register

STOP = 1 ?

ICSR register

TDRE bit

← 0

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(12)

(10)

(13)

(14)

(11)

(9)

(15)

ICIER register

ACKBT bit

← 0

Yes

Read ICDRR register

ICIER register

ACKBT bit

← 1

ICCR1 register

RCVD bit

← 1

Read ICDRR register

Read RDRF bit in ICSR register

RDRF = 1 ?

Read ICDRR register

ICCR1 register

RCVD bit

← 0

ICCR1 register

MST bit

← 0

Yes

NOTES:

1. Do not generate the interrupt during the process of step (1) to (3).

2. When receiving 1 byte, skip step (2) to (6) after (1) and jump to process of step (7).

Process of step (8) is dummy-read in the ICDRR register.

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