CC1150-RTY1 datasheet(55/67 Pages) TI1

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CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

6.2.4

Reference Signal

The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This

input clock can either be a full-swing digital signal (0 V to VDD) or a sine wave of maximum 1-V peak-to-

peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be

connected to XOSC_Q1 using a serial capacitor. The XOSC_Q2 line must be left unconnected. C51 and

C71 can be omitted when using a reference signal.

6.2.5

Additional Filtering

In the 868/915 MHz reference design, C106 and L105 together with C105 build an optional filter to reduce

emission at 699 MHz. This filter may be necessary for applications seeking compliance with ETSI EN 300-

220, for more information, see DN017 [6]. If this filtering is not necessary, C105 will work as a DC block

(only necessary if there is a DC path in the antenna). C106 and L105 should in that case be left

unmounted.

Additional external components (for example, an RF SAW filter) may be used in order to improve the

performance in specific applications. The use of wire-wound inductors in the application circuit will also

improve the RF performance and give higher output power. For more information, see DN017 [6].

6.2.6

Power Supply Decoupling

The power supply must be properly decoupled close to the supply pins.

NOTE

Decoupling capacitors are not shown in the application circuit. The placement and the size of

the decoupling capacitors are very important to achieve the optimum performance.

The CC1150EM reference design should be followed closely (see [1] and [2]).

6.3

PCB Layout Recommendations

The top layer should be used for signal routing, and the open areas should be filled with metallization

connected to ground using several vias.

The area under the chip is used for grounding and shall be connected to the bottom ground plane with

several vias for good thermal performance and sufficiently low inductance to ground.

In the CC1150EM reference designs (see [1] and [2]), 5 vias are placed inside the exposed die attached

pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid

migration of solder through the vias during the solder-reflow process.

The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process,

which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste

coverage below 100%. See Figure 6-4 for top solder resist and top paste masks.

All the decoupling capacitors should be placed as close as possible to the supply pin it is supposed to

decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate

vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the

CC1150 supply pin. Supply power filtering is very important.

Applications, Implementation, and Layout

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