CC1150-RTY1 datasheet(39/67 Pages) TI1

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CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

Figure 5-19 summarizes the SPI address space. Registers that are only defined on the CC1101

transceiver are also listed. CC1101 and CC1150 are register compatible, but registers and fields only

implemented in the transceiver always contain 0 in CC1150.

The address to use is given by adding the base address to the left and the burst and read/write bits on the

top. Note that the burst bit has different meaning for base addresses above and below 0x2F.

Table 5-11. Command Strobes

ADDRESS

STROBE NAME

DESCRIPTION

0x30

SRES

Reset chip.

0x31

SFSTXON

Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).

0x32

SXOFF

Turn off crystal oscillator.

0x33

SCAL

Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed in

IDLE state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)

0x35

STX

Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.

0x36

SIDLE

Exit TX and turn off frequency synthesizer.

0x39

SPWD

Enter power down mode when CSn goes high.

0x3B

SFTX

Flush the TX FIFO buffer.

0x3D

SNOP

No operation. May be used to pad strobe commands to two bytes for simpler software.

Table 5-12. Configuration Registers Overview

ADDRESS

ACRONYM

SECTION

0x01

IOCFG1

GDO1 output pin configuration

Table 5-14

0x02

IOCFG0

GDO0 output pin configuration

Table 5-15

0x03

FIFOTHR

FIFO threshold

Table 5-16

0x04

SYNC1

Sync word, high byte

Table 5-17

0x05

SYNC0

Sync word, low byte

Table 5-18

0x06

PKTLEN

Packet length

Table 5-19

0x08

PKTCTRL0

Packet automation control

Table 5-20

0x09

ADDR

Device address

Table 5-21

0x0A

CHANNR

Channel number

Table 5-22

0x0D

FREQ2

Frequency control word, high byte

Table 5-23

0x0E

FREQ1

Frequency control word, middle byte

Table 5-24

0x0F

FREQ0

Frequency control word, low byte

Table 5-25

0x10

MDMCFG4

Modulator configuration

Table 5-26

0x11

MDMCFG3

Modulator configuration

Table 5-27

0x12

MDMCFG2

Modulator configuration

Table 5-28

0x13

MDMCFG1

Modulator configuration

Table 5-29

0x14

MDMCFG0

Modulator configuration

Table 5-30

0x15

DEVIATN

Modulator deviation setting

Table 5-31

0x17

MCSM1

Main Radio Control State Machine configuration

Table 5-32

0x18

MCSM0

Main Radio Control State Machine configuration

Table 5-33

Detailed Description

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